1. Field of the Invention
The present invention relates to a solid-state imaging device, a pixel-signal processing method for a solid-state imaging device, an analog-signal transferring device, and an analog-signal transferring method.
2. Description of the Related Art
Recently, as an alternative to CCD image sensors, interest in CMOS image sensors has arisen. This is because CMOS image sensors overcome various problems of CCD image sensors. The problems of CCD image sensors include, for example, the problem that CCD requires special processes for manufacturing, the problem that a plurality of power supply voltages is needed for operation thereof, and the problem that the system is very complex since a plurality of peripheral ICs must be used in combination.
CMOS image sensors can be manufactured by the same manufacturing processes as ordinary CMOS integrated circuits that are manufactured around the world. Furthermore, CMOS image sensors can be driven by a singe power source. Furthermore, it is possible to combine analog circuits and logic circuits manufactured by CMOS processes in a single chip, so that the number of peripheral ICs can be reduced. These are considerable merits for the CMOS image sensors.
The mainstream of output circuits for CCDs is one-channel output using a floating diffusion (FD) amp. In contrast, the mainstream of CMOS image sensors is of the type having FD amps for respective pixels and having column-parallel outputs, i.e., one row of a pixel array is selected and pixels on the selected row are simultaneously read out in a column direction. In this type of CMOS image sensors, it is difficult to obtain sufficient driving ability with the FD amps provided in the pixels, so that the data rate must be decreased, for which parallel processing is advantageous.
Various arrangements of a signal output circuit for the parallel-output CMOS image sensors have been proposed. As an example, outputs of pixels are sampled by switched capacitors to read the outputs. As another example, signals are read by amps provided for the respective columns. As yet another example, AD converters and DRAMs are also provided for the respective columns. The present invention mainly relates to a scheme of reading by amps provided for the respective columns.
Japanese Unexamined Patent Application Publication No. 5-207220 describes an example of the scheme of reading by amps provided for the respective columns, which will be briefly described with reference to FIGS. 16 and 17.
In, FIG. 16, one column (circuitry of one vertical signal line VL) associated with one pixel 102 is shown as extracted.
The pixel 102 is formed by a photodiode PD, a reset transistor Trst, an amplifying transistor Tg, and a reading transistor Ts. In this case, the output of the pixel 102 is read using a charge integrating amp formed by a source-grounded amp 100 and capacitors C1 and C2.
It is to be particularly noted that the feedback capacitor C2 is adapted to be precharged by a switch Tr15 and a reference voltage Vref so that offset variation among the source-grounded amps 100 is removed.
FIG. 17 shows an operation timing chart of the circuit. In a period T1 in a horizontal blanking period, a value obtained by superposing a signal Vps on an offset voltage Vo is output. The charge integrating amp is reset with a switch Tr13 turned off by a signal φRC. At this time, the switch Tr15 is turned on by the signal φRC, and the switch Tr14 is turned off by a signal φTC, so that the capacitor C2 is precharged to the reference voltage Vref.
Then, in a period T2, the switch Tr15 is turned off and the switch Tr14 is turned on by the signals φRC and φTC, so that the precharged reference voltage Vref appears on the output of the charge integrating amp. Since the switch Tr13 is turned off simultaneously with the switch Tr15, the reset state is exited.
Then, in a period T3, only the offset voltage Vo is output from the pixel 102, and the output is integrated, so that only the signal component is read at the output of the charge integrating amp with a gain determined by the capacitance ratio of the capacitors C1 and C2.
The signals that are read last are sequentially output to the horizontal signal lines HL in synchronization with pulses supplied from a shift register 101.
As described above, according to the scheme of reading by amps provided for the respective columns, it is readily possible to remove an offset voltage of pixels and to extract only signal components, and the gain of reading can be set arbitrarily by the capacitance ratio of the capacitors C1 and C2. Furthermore, variation of source follower can be removed by precharging of the reference voltage Vref. As described above, the scheme has various advantages.
Japanese Unexamined Patent Application Publication No. 11-266399 describes another scheme of reading, which will be described with reference to FIGS. 18 and 19.
In FIG. 17, three columns (vertical signal lines VL1, VLn, and VLN) that are arbitrarily selected are shown as extracted. Furthermore, as a pixel 200 formed by a photodiode PD and a reading transistor Ts, a pixel associated with a selecting line Vs is shown. In this case, when the selecting line Vs is selected by a vertical scanning circuit 201, pixels on one row are selected, and signals from the respective pixels are output to the respective columns (the respective vertical signal lines VL).
This example is similar to the example described in Japanese Unexamined Patent Application Publication No. 5-207220 in that amps 203 are provided for the respective columns (the respective vertical signal lines VL). It is to be particularly noted, however, that standby controlling signals φP (φP1, φPn, and φPN) are supplied from a horizontal scanning circuit 202 to the respective amps 203. Thus, the amps 203 are allowed to shift between a standby state and an active state on a column-by-column basis.
The outputs of the respective amps 203 are selected by switches 204, and are transferred to an output terminal 205 via horizontal signal lines HL. The switches 204 are respectively controlled to turn on or off by signals φH (φH1, φHn, and φHN) from the horizontal scanning circuit 202.
FIG. 19 shows an operation timing chart.
An amp 203 is selected by a pulse of the signal φHN, and a signal is read in that period. As opposed to the example described in Japanese Unexamined Patent Application Publication No. 5-207220, signals are not read at once in a horizontal blanking period, but signals are respectively read in periods selected according to the signals φHN, so that operation is not needed in periods not selected according to the signals φHN. That is, amps 203 that are not selected are allowed to stay in the standby state.
Considering that it takes some time for the amps 203 to return from the standby state, standby control signals φPn are caused to rise somewhat earlier than the signals φHn, but the amps are in the standby state in other periods so that currents do not flow. Thus, for example, assuming a sensor (pixel array) having 1,000 columns and the amps 203 provided for the respective columns, a current actually flows only in one amp, or two amps in the example shown in FIG. 19 considering overlapping of the signals φPn. Thus, advantageously, power consumption is very low.
The related art described in Japanese Unexamined Patent Application Publication No. 5-207220 and Japanese Unexamined Patent Application Publication No. 11-266399 have the following problems.
According to Japanese Unexamined Patent Application Publication No. 5-207220, since amps must be provided for the respective columns, power consumption inevitably increases. Particularly in this example, horizontal signal lines HL must be driven directly, and for example, in the case of a sensor having 1,000 columns, the time that can be used to drive the horizontal signal lines HL is limited to 1/1,000 of an effective period of a horizontal period, so that operation at a very high speed is required. This causes increase in operation current per one amp among the amps provided for the respective columns, causing additional increase in power consumption.
Furthermore, although the reference voltage Vref essentially determines the black level of signals, since a fixed potential is used, tracking ability to variation factors such as temperature change or power supply voltage is not provided. Thus, a clamp circuit is needed at a subsequent stage in order to supply a stable black level, causing increase in circuitry scale.
According to Japanese Unexamined Patent Application Publication No. 11-266399, although power consumption is decreased, as described earlier, pixel signals must be read and horizontally transferred in the periods of the signals φHn. Thus, compared with the example described in Japanese Unexamined Patent Application Publication No. 5-207220, the amps must operate at a very high speed, causing increase in current that flows per one amp. Furthermore, the layout area of the amps increases, which is very disadvantageous considering the restriction that the amps must be laid out respectively for the vertical signal lines from the imaging pixel array, i.e., for the respective columns, so that difficulty is design is expected.